Responsible to provide technical leadership across projects in area of pre silicon and post silicon validation must be able to juggle multiple threads and projects and be recognized as an expert by an extended team withi
Design and Execute IO layout from floor plan to placement for multiple application.Layout Designing in the modules of GPIO DDR LVDS USB.RequirementsHands on experience in IO layout.Hands on layout experience in the modul
Design and Verification of Power Management modules like LDO DCDC sub modules Bandgaps Temperature sensor POR etc for SOC.Also needs to interact with Layout Engineer for proper Layout closure.RequirementsStrong in CMOS b
Completely own and carry out high speed SerDes IPs for consumer and telecom applications. These projects can either be new development from scratch or re targeting current IPs to new process technologies.Work with custom
Hands on work experience in Digital Physical Design PD at Full Chip Level SoC or IP Level in technologies of nm and below nm nm Exposure to IP Hardening for blocks like SERDES USB PHY MIPI SATA will be an added advantage
Create support and maintain CAD scripts and tools.You will debug and address tool problems raised by the design and layout communities.You will be involved in CAD tool evaluations and CAD project execution.RequirementsKn
Lead a team for Design and Verification of Power Management modules like LDO DCDC PLL sub mudules Bandgaps Temperature sensor POR etc for SOC.Need to interact with Layout Engineer for proper Layout closure.RequirementsSt
Experience of advanced custom circuit implementations.Good understanding of SRAM architecture Critical Path Modelling Full Cut Analysis Marginality Analysis and Monte Carlo Simulations.Exposure to full embedded memory de
Completely own and carry out PHY development projects either from scratch or from available projects in other nodes porting .Work with customer engineering and internal sales or pre sales technically to determine customi
Exposure development exp with Linux working environment prior experience in device driver development is a plusWorking experience in Matrix organizations managing deliverables dependencies with cross functional multi sit
Skill Requirements Hands on in Verilog VHDLHands on in Perl Unix scriptingHands on in SoC level RTL integrationHands on in Clock Domain Crossing CDC checks Linting equivalence checksExperience in Digital module micro arc
Hands on work experience in Digital Physical Design PD at Full Chip Level SoC or IP Level in technologies of nm and below nm nm Exposure to IP Hardening for blocks like SERDES USB PHY MIPI SATA will be an added advantage
Priority of languages . Perl SKILL. TCL Python. C C Needs to be aware of best practices complex SW development not just pure automation. Should be able to create professional SW using design paradigms data flow diagrams
Thorough in Analog basics. Experties in various IO design such as VML CML and LVDS. Good knowledge in PLL SERDES is required. Work experience on various serial IO standards such as DP HDMI MIPI etc is a plus.
Drive revenue within key accounts within the territory. Identify prospect and qualify new opportunities to grow revenue.Work closely with marketing and take advantage of their programs to maximize new opportunities devel
Bangalore, or Bengaluru as it is now known, is the city with its roots deep in history and its vision set firmly on the future. One of the biggest metropolitan cities in India, it stands fourth after Mumbai, Delhi and Kolkata. ‘The City of Gardens’ or the ‘Silicon Valley of India’, Bangalore is known by many nicknames, each of which demonstrates a defining characteristic of this thriving cosmopolitan city. Visionary administrative policies, adequate public infrastructure and an abundance of premier education institutes, contributed to the ascension of Bangalore to the go-to destination for ca...
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